This invention relates generally to the field of integrated circuit fabrication, and in particular the invention relates to reducing the coupling capacitance between closely spaced electrically conductive interconnect lines, or in other words reducing the effective dielectric constant of the material between closely spaced electrically conductive interconnect lines.
During fabrication of an integrated circuit, a variety of layers of electrically insulating materials and electrically conducting materials are typically deposited on a substrate. The layers are patterned by selectively removing portions of the layers, to form the desired electrical circuits. The need for faster and more complex integrated circuits provides incentive to decrease the size of the integrated circuits. As the size of the integrated circuit decreases, the size of the electrically conductive interconnects between the various components of the integrated circuit also tends to decrease. For proper performance of the integrated circuit, it is desirable to maintain high reliability and low electrical resistance while decreasing both the size of the electrical interconnects and the spacing between adjacent electrical interconnects.
Highly conductive materials, such as metals, are often used for forming the electrically conductive interconnect lines of integrated circuits. As the size of and spacing between the electrically conductive interconnect lines decreases, the capacitance between closely spaced interconnects tends to increase, causing a generally commensurate increase in cross talk and power dissipation between adjacent interconnect lines. Cross talk is the signal interference between electrically conductive interconnect lines, which tends to adversely affect signal integrity and signal strength. Power dissipation is the dynamic power drained by unwanted capacitance charging and discharging in a circuit.
What is needed, therefore, is a method for reducing coupling capacitance between adjacent electrically conductive interconnect lines in an integrated circuit.
These and other needs are provided by a method for reducing the coupling capacitance between electrically conductive interconnect lines of an integrated circuit. A conductive layer is deposited on a substrate, and etched to define electrically conductive interconnect lines having negatively sloped sidewalls. The negatively sloping sidewalls of adjacent electrically conductive interconnect lines form undercut gaps in the conductive layer. An insulating layer is deposited on the etched conductive layer using a directional physical vapor deposition to cover the undercut gaps and form a void in each of the undercut gaps. The void is directly adjacent the negative sloping sidewalls of adjacent electrically conductive interconnect lines.
In another aspect the invention provides an integrated circuit having closely spaced electrically conductive interconnect lines. A void is formed between and directly adjacent undercut sidewalls of adjacent electrically conductive interconnect lines. The void preferably has a dielectric constant that is less than about two.
An advantage of the invention is. that it provides an integrated circuit having air gaps between electrically conductive interconnect lines so that more closely spaced interconnect lines can be provided on a substrate surface. Furthermore, the dielectric constant of the void between adjacent interconnect lines tends to be substantially lower than those of the insulating materials that are typically used, such as silicon oxide. Because of the negatively sloping sidewalls of the adjacent interconnect lines, the void space in the gap is preferably relatively high, resulting in a relatively small effective dielectric constant, which in turn results in a substantially lower effective capacitance between adjacent electrically conductive interconnect lines.